This application relates generally to computer compilers. More specifically, this application relates to methods and systems for compiling multi-threaded applications for targeted criticalities.
For a number of decades, improvements in microprocessor performance have been realized at exponential rates. This has largely been a consequence of exploiting ever-increasing transistor budgets, which have allowed computer architects to increase processor frequency and instructions per cycle (“IPC”). But while Moore's law remains valid, diminishing returns are now being realized from conventional processor-design techniques, resulting in increased interest in alternative approaches for continuing to achieve performance gains.
Conventional compilers act to compile applications in a uniform way by assuming that all application threads have access to the same resources. Because of this, the full benefit of critical thread marking, which provides different resources to different application threads, is unrealized. For example, if a particular application spawns many threads that will run in parallel, or if other application threads share the core resources, then the binary code generated by the compiler is sub-optimal for the throughput environment. In such a throughput environment, instruction latencies can be covered by the execution of instructions from different threads or applications, so there is no need for the instruction scheduler to use full instruction latencies when scheduling instructions. Using full instruction latencies could increase the number of spills and reloads producing a binary that is less optimal.
This application accordingly discloses compiler methods that improve performance in a mixed serial and throughput execution environment.